 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PJSMF03LC Series 5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION This 5-TVS/Zener Array has been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry, operating at 3.3V and 5V, as well available for 12V, 15V, and 24V Systems. This TVS array offers an integrated solution to protect up to 5 data lines where the board space is a premium. SPECIFICATION FEATURES 100W Power Dissipation (8/20s Waveform) Low Leakage Current Very Low Clamping Voltage IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance Operating voltage options for 3.3V, 5V, 12V, 15V, and 24V Industry Standard SOT363 (SC70-6L) Package 1 6 5 4 APPLICATIONS Personal Digital Assistant (PDA) SIM Card Port Protection (Mobile Phone) Portable Instrumentation Mobile Phones and Accessories Memory Card Port Protection 1 2 3 SOT363 MAXIMUM RATINGS (Per Device) Rating Peak Pulse Power (8/20s Waveform) ESD Voltage (HBM) Operating Temperature Range Storage Temperature Range Symbol P pp V ESD TJ Tstg Value 100 25 -55 to +150 -55 to + 150 Units W kV C C ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25C PJSMF03LC Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (820s) Clamping Voltage (8/20s) Off State Junction Capacitance Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj Cj I BR = 10 mA VR = 3.3V I pp = 5A I pp = 9A 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 3.3 Vdc Bias f = 1MHz Between I/O pins and pin 2 Conditions Min Typical Max 3.3 Units V V A V V pF pF 4.7 5.6 250 7.5 9 160 90 9/14/2005 Page 1 www.panjit.com PJSMF03LC Series ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25C PJSMF05LC Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Clamping Voltage (8/20s) Off State Junction Capacitance Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj Cj I BR = 1mA VR = 5V I pp = 5A I pp = 9A 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 5 Vdc Bias f = 1MHz Between I/O pins and pin 2 Conditions Min Typical Max 5 Units V V 6.2 0.5 10 11 100 45 A V V pF pF PJSMF12LC Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Clamping Voltage (8/20s) Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj I BR = 1mA VR = 12V I pp = 3A I pp = 5A 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 Conditions Min Typical Max 12 Units V V 13.3 0.5 18 20 50 A V V pF PJSMF15LC Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Clamping Voltage (8/20s) Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj I BR = 1mA VR = 15V I pp = 3A I pp = 4A 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 Conditions Min Typical Max 15 Units V V 16.6 0.5 23 25 40 A V V pF 9/14/2005 Page 2 www.panjit.com PJSMF03LC Series ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25C PJSMF24LC Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Clamping Voltage (8/20s) Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj I BR = 1mA VR = 24V I pp = 1A I pp = 2A 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 Conditions Min Typical Max 24 Units V V 26.7 0.5 35 45 30 A V V pF PJSMF36LC Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Clamping Voltage (8/20s) Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj I BR = 1mA VR = 36V I pp = 1A I pp = 2A 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 Conditions Min Typical Max 36 Units V V 38 0.5 40 50 25 A V V pF 9/14/2005 Page 3 www.panjit.com PJSMF03LC Series TYPICAL CHARACTERISTICS 25C unless otherwise noted Non-Repetitive Peak Pulse Power vs Pulse Time 1000 Pulse Waveform 110 100 90 80 70 60 50 40 30 20 10 0 0 Peak Pulse Power - Ppp (W) 100 Percent of Ipp 50% of Ipp @ 20s R tim 10-90% - 8s ise e 10 1 10 100 1000 Pulse Duration, sec 5 10 15 20 25 30 time, sec Capacitance vs. Biasing Voltage @1MHz 100 90 Capacitance, pF Typical Leakage Current vs Temperature Clamping Voltage vs Ipp 8x20sec Surge 0.1000 10 9 8 0.0100 7 6 5 4 0.0010 3 2 1 0 0.0001 PJSMF05LC 5V 80 70 60 50 40 30 Ipp, Amps Current, A PJSMF05LC 3V 6 25 7 50 8 75 Temp,C 9 100 10 125 11 150 0 1 2 3 4 5 Clamping Voltage, V Bias Voltage, Vdc 9/14/2005 Page 4 www.panjit.com PJSMF03LC Series LAYOUT DIMENSIONS AND SUGGESTED PAD LAYOUT 9/14/2005 Page 5 www.panjit.com |
Price & Availability of PJSMF15LC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |